Data buffering: Because the speed of the I/O device is low and the speed of the CPU and memory is very high, a buffer must be set in the controller. When outputting, use this buffer to temporarily store data from the host at high speed, and then transfer the data in the buffer to the I/O device at the rate that the I/O device has; when inputting, the buffer is used To temporarily store the data sent from the I/O device, after receiving a batch of data, the data in the buffer is transmitted to the host at a high speed.
Error control: The device controller is also responsible for error detection on the data transmitted by the I/O device. If an error is found in the transmission, the error detection code is usually set and reported to the CPU, so the CPU invalidates the data transmitted this time and transmits it again. In this way, the correctness of data input can be guaranteed.
Data exchange: This refers to the realization of data exchange between the CPU and the controller, and between the controller and the device. For the former, through the data bus, the CPU writes data to the controller in parallel, or reads data from the controller in parallel; for the latter, the device inputs data to the controller or transmits data from the controller to the device . For this reason, the data register must be set in the controller.
Status description: The status controller that identifies and reports the device should record the status of the device for the CPU to understand. For example, only when the device is in the ready to send state, the CPU can start the controller to read data from the device. For this reason, a status register should be set up in the controller, and each bit of it is used to reflect a certain status of the device. When the CPU reads the contents of this register, it can understand the status of the device.
Receiving and recognizing commands: The CPU can send a variety of different commands to the controller, and the device controller should be able to receive and recognize these commands. For this reason, there should be corresponding control registers in the controller to store the received commands and parameters, and to decode the received commands. For example, the disk controller can receive 15 different commands such as Read, Write, Format, etc. from the CPU, and some commands also carry parameters; accordingly, there are multiple registers and command decoders in the disk controller.
Address recognition: Just as every unit in the memory has an address, every device in the system also has an address, and the device controller must be able to identify the address of each device it controls. In addition, in order to enable the CPU to write (or read) data to (or from) the registers, these registers should all have unique addresses.